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[SourceCode] DCT实现Verilog HDL的数字图像处理源代码

Description: DCT实现Verilog HDL的数字图像处理
Platform: | Size: 31657 | Author: juyong | Hits:

[VHDL-FPGA-Verilog] Verilog HDL Examples

Description: verilog的入门级别的例子（转载）-Verilog entry-level examples (reproduced)
Platform: | Size: 87040 | Author: 周贤 | Hits:

[VHDL-FPGA-Verilog] Computer Architecture Handbook on Verilog HDL

Description: Computer Architecture Handbook on Verilog HDL
Platform: | Size: 66560 | Author: 路路 | Hits:

[VHDL-FPGA-Verilog] verilog SDRAM core

Description: 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
Platform: | Size: 27648 | Author: 于飞 | Hits:

[Other] cpu的VERILOG描述

Description: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
Platform: | Size: 369664 | Author: 陈俊 | Hits:

[Other Embeded program] trafficLight-verilog

Description: 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
Platform: | Size: 1532928 | Author: 王越 | Hits:

[Embeded-SCM Develop] verilog.HDL.examples

Description: 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
Platform: | Size: 188416 | Author: 张驰 | Hits:

[Other] TW-Verilog

Description: 台湾verilog hdl硬件描述性语言，适合有基础的人-Taiwan verilog hdl hardware description language, suitable for those who have the basis of
Platform: | Size: 1412096 | Author: josh915 | Hits:

[Other] verilog

Description: 一个介绍verilog HDL的ppt文档，包括全部的22章。-Verilog HDL a presentation of ppt documents, including all of Chapter 22.
Platform: | Size: 1549312 | Author: 林熙鹏 | Hits:

[Other] Verilog-PPT

Description: Verilog HDL语言的PPT教程。包括简介、逻辑概念、语法和示例。-Verilog HDL language tutorial PPT. Including profiles, the logic of concepts, syntax and examples.
Platform: | Size: 536576 | Author: 翟红光 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 北大微电子学系于敦山老师的课件，介绍Verilog HDL、Cadence Verilog仿真器、可综合的Verilog HDL、设计举例、自动布局布线工具、Verilog的词汇约定等内容-Department of Microelectronics, Peking University in the teacher s courseware mts on Verilog HDL, Cadence Verilog simulator can be integrated Verilog HDL, design, for example, automatic placement and routing tools, Verilog, etc. terms agreed
Platform: | Size: 1550336 | Author: 唐进 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 是几个用Verilog HDL语言编写的源代码（里面包括实现滤波器等），对想学习这个语言的朋友很有帮助！ -Several languages to use Verilog HDL source code (which includes the realization of filters, etc.), to want to learn this language very helpful friend!
Platform: | Size: 14336 | Author: 吴雨彤 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 本书简要介绍了Verilog硬件描述语言的基础知识，包括语言的基本内容和基本结构 ，以及利用该语言在各种层次上对数字系统的建模方法。书中列举了大量实例，帮助读者掌握语言本身和建模方法，对实际数字系统设计也很有帮助。本书是Verilog HDL的初级读本，适用于作为计算机、电子、电气及自控等专业相关课程的教材，也可供有关的科研人员作为参考书。 -The book briefly introduce the Verilog hardware description language of the basic knowledge, including the basic elements of language and basic structure, and the use of the language at various levels of digital system modeling method. The book lists a large number of examples to help readers master the language itself and modeling methods, the actual number of system design is also very helpful. This book is the Verilog HDL Primer, apply to as computers, electronics, electrical and control-related courses and other specialized materials, also available to the researchers as a reference.
Platform: | Size: 4171776 | Author: 张文辉 | Hits:

[VHDL-FPGA-Verilog] Verilog--shiyanbaogao

Description: 有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的. 练习三 利用条件语句实现计数分频时序电路 实验目的： 1. 掌握条件语句在简单时序模块设计中的使用； 2. 学习在Verilog模块中应用计数器； 3. 学习测试模块的编写、综合和不同层次的仿真。 练习四 阻塞赋值与非阻塞赋值的区别 实验目的： 1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别； 2． 了解阻塞赋值与非阻塞赋值的不同使用场合； 3． 学习测试模块的编写、综合和不同层次的仿真。 -The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment using different occasions 3. Test the preparation of learning modules, integrated and different levels of simulation.
Platform: | Size: 15360 | Author: 盼盼 | Hits:

[VHDL-FPGA-Verilog] Verilog-book

Description: 学习Verilog语言必备资料，包括语法总结 编写Verilog HDL 源代码的标准及设计流程-Verilog language learning essential information, including syntax summary of Verilog HDL source code for the preparation of standards and design process
Platform: | Size: 3835904 | Author: shaoyqo | Hits:

[VHDL-FPGA-Verilog] Mars_EP1C6F_Fundermental_demo(Verilog)

Description: FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
Platform: | Size: 1244160 | Author: chenlu | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 中文版Verilog HDL简明教程，很简洁，结合实例，很容易理解，适合初学者。-Chinese version of Verilog HDL A simple tutorial, very simple, with an example, it is easy to understand for beginners.
Platform: | Size: 104448 | Author: 邹仁波 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 通过I2C接口读写EEPROM 在本项目中，我们利用Verilog HDL实现了部分I2C总线功能，并能够通过该总线对AT24C02进行读写操作。为了便于观察读写eeprom的结果，我们将读写的数据同时显示在七段数码管上，并设定读写的数据从0到255不断循环，这样就可以方便进行比较。 -Through the I2C interface to read and write EEPROM in this project, we use Verilog HDL to achieve some of the I2C bus function, and can be carried out through the bus, read and write operations on the AT24C02. To read and write eeprom in order to facilitate observation of the results, we will read and write data simultaneously displayed in the seven-segment digital tube, and set read and write data from 0 to 255 in cycles, so that can be easily compared.
Platform: | Size: 8192 | Author: andy | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: 《北航常晓明Verilog应用》一书的pdf完整版，是学习Verilog的好书-" Beihang Chang Xiaoming Verilog Applications" pdf full version of the book is a good book to learn Verilog
Platform: | Size: 15432704 | Author: 甘福连 | Hits:

[source in ebook] 《Verilog HDL设计与实战》配套代码（2）

Description: 《Verilog HDL设计与实战》配套代码 (2)("Verilog HDL design and actual combat" matching code (2))
Platform: | Size: 103367680 | Author: 铭铭扬扬 | Hits:
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